The present invention relates to a memory accessing circuit, especially a multi-state accessing circuit for accessing 4 or more states.
A known magnetic random access memory having 4 states is comprised of one large memory cell and one small memory cell as shown in FIG. 5A. By changing the magnetized polarities of the magnetized memory layers, resistors R1 and R2 can change resistance of the memory cell. Because the logic state of the memory cells having different resistances for 0 and 1, when applying bias to the memory cells, different currents are generated. By determining the value of the currents, the logic state of the memory cells being 0 or 1 can be determined.
Also, memory cell accessing rates are closely related to a sense amplifier. The faster for the sense amplifier determines the state of the memory cell, the better it is. The time it takes to determine the state of the memory cell is also related to the value of the current.
As shown in FIG. 5B, when the resistors R1 and R2 are connected in parallel, there are 4 variations, R1max//R2max, R1max//R2min, R1min//R2max, R1min//R2min, for representing 4 stored states 11, 10, 01, 00. Because a 4-state magnetic random accessing memory has 4 different resistance variations, when applied with constant direct current, 4 different memory currents can be generated.
In order to determine the stored state of the magnetic random accessing memory, the magnetic random accessing memory generates at least 3 sets of base values for comparing with the memory current of the magnetic random accessing memory to generate one of 4 comparison results and to determine the stored state of the magnetic random accessing memory.
As shown in FIG. 7, an accessing circuit has 3 reference paths for representing 3 different impedance levels [(Iref3: R1max//R2max//R1max//R2min), (Iref2: R1max//R2min//R1min//R2max), (Iref1: R1min//R2max//R1min//R2min)] and generating 3 reference currents (IREF1, IREF2, and IREF3). By comparing the reference currents with the memory current, the most significant bit (MSB) D1 and the least significant bit D0 can be generated.
When a memory has more memory states (4 or more), the memory accessing circuit needs more reference paths. Because each reference path is comprised of multiple sets of resistors, more reference paths result in larger area of memory accessing circuits and greater power consumption.